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Intel® Xeon® Processor 7400 Series Datasheet 41
Electrical Specifications
2.14 Processor AC Timing Waveforms
The following figures are used in conjunction with the AC timing tables, Table 2-19
through Table 2-25.
Note: For Figure 2-8 through Figure 2-21, the following apply:
1. All common clock AC timings for AGTL+ signals are referenced to the Crossing
Voltage (V
CROSS
) of the BCLK[1:0] at rising edge of BCLK0. All common clock
AGTL+ signal timings are referenced at nominal GTLREF_DATA_MID,
GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END at the processor
pads.
2. All source synchronous AC timings for AGTL+ signals are referenced to their
associated strobe (address or data) at nominal GTLREF_DATA_MID,
GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END. Source
synchronous data signals are referenced to the falling edge of their associated data
strobe. Source synchronous address signals are referenced to the rising and falling
edge of their associated address strobe. All source synchronous AGTL+ signal
timings are referenced at nominal GTLREF_DATA_MID, GTLREF_DATA_END,
GTLREF_ADD_MID, and GTLREF_ADD_END at the processor pads.
3. All AC timings for AGTL+ strobe signals are referenced to BCLK[1:0] at V
CROSS
. All
AGTL+ strobe signal timings are referenced at nominal GTLREF_DATA_MID,
GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END at the processor
pads.
4. All AC timings for the TAP signals are referenced to the TCK at 0.5 * V
TT
at the
processor pins. All TAP signal timings (TMS, TDI, etc...) are referenced at 0.5 * V
TT
at the processor pads.
5. All CMOS signal timings are referenced at 0.5 * V
TT
at the processor pins.
6. All AC timings for the SMBus signals are referenced to the SM_CLK at 0.5 *
SM_VCC at the processor pins. All SMBus signal timings (SM_DAT, SM_CLK, etc.)
are referenced at
The circuit used to test the AC specification is shown in Figure 2-7.
3. Rise time is measured from (V
IL_MAX
- 0.15V) to (V
IH_MIN
+ 0.15V). Fall time is measured from
(0.9*SM_VCC) to (V
IL_MAX
- 0.15V). DC parameters are specified in Table 2-26.
4. Minimum time allowed between request cycles.
5. Following a write transaction, an internal write cycle time of 10ms must be allowed before starting the next
transaction.
Figure 2-7. Electrical Test Circuit
V
TT
48 ohms, 169 ps/in, 1200 mils
L = 1.475 nH
C = 0.85 pF
V
TT
R
LOAD
AC Timings specified at this
point
Buffer
- Datasheet 1
- Contents 3
- Revision History 7
- 1 Introduction 9
- 1.1 Terminology 11
- Introduction 12
- 1.2 State of Data 13
- 1.3 References 13
- 2 Electrical Specifications 15
- 2.2 Decoupling Guidelines 16
- Clocking 16
- 2.3.2 PLL Power Supply 18
- Electrical Specifications 20
- Table 2-4. FSB Signal Groups 21
- Asynchronous Signals 22
- 2.9 Mixing Processors 23
- Time Duration (s) 28
- Sustained Current (A) 28
- Table 2-10. V 30
- Figure 2-4. V 31
- 2.11.2 V 33
- Overshoot Specification 33
- 2.11.3 Die Voltage Validation 33
- 2.11.4.1 DC Characteristics 34
- 2.12 AGTL+ FSB Specifications 35
- Tp = T1: BCLK[1:0] period 42
- THERMTRIP# 46
- System bus 48
- FERR#/PBE# 48
- Figure 2-22. VID Step Timings 49
- 3 Mechanical Specifications 51
- Mechanical Specifications 52
- 3.7 Processor Materials 61
- 3.8 Processor Markings 62
- Processor 63
- 4 Pin Listing 65
- (Sheet 3 of 16) 66
- (Sheet 4 of 16) 66
- (Sheet 5 of 16) 67
- (Sheet 6 of 16) 67
- (Sheet 7 of 16) 68
- (Sheet 8 of 16) 68
- (Sheet 9 of 16) 69
- (Sheet 10 of 16) 69
- (Sheet 11 of 16) 70
- (Sheet 12 of 16) 70
- (Sheet 13 of 16) 71
- (Sheet 14 of 16) 71
- (Sheet 15 of 16) 72
- (Sheet 16 of 16) 72
- (Sheet 1 of 14) 73
- (Sheet 2 of 14) 73
- (Sheet 3 of 14) 74
- (Sheet 4 of 14) 74
- (Sheet 5 of 14) 75
- (Sheet 6 of 14) 75
- (Sheet 7 of 14) 76
- (Sheet 8 of 14) 76
- (Sheet 9 of 14) 77
- (Sheet 10 of 14) 77
- (Sheet 11 of 14) 78
- (Sheet 12 of 14) 78
- (Sheet 13 of 14) 79
- (Sheet 14 of 14) 79
- Pin Listing 80
- 5 Signal Definitions 81
- FSB agents 85
- . The processor includes 86
- 6 Thermal Specifications 89
- CASE_MAX 90
- CASE (°C) 91
- = 0.431 x Power + 45 95
- Power (W) 96
- Temperature (C) 96
- 6.1.2 Thermal Metrology 97
- 6.2.2 Intel Thermal Monitor 97
- 6.2.3 Intel Thermal Monitor 2 98
- 6.2.4 On-Demand Mode 99
- 6.2.5 PROCHOT# Signal 100
- 6.2.6 FORCEPR# Signal 100
- 6.2.7 THERMTRIP# Signal 100
- 6.3.1 Introduction 101
- 6.3.1.1 T 102
- 6.3.2.1 PECI Device Address 103
- 6.3.2.2 PECI Command Support 103
- 7 Features 105
- 7.2.2.1 HALT State 106
- 7.2.2.2 Extended HALT State 106
- 7.2.3 Stop-Grant State 108
- 7.3 Enhanced Intel SpeedStep 109
- Technology 109
- Features 110
- 7.4.1 SMBus Device Addressing 111
- Transactions 112
- 7.4.3.1 Header 115
- 7.4.3.2 Processor Data 119
- 0Eh-13h 120
- 7.4.3.3 Processor Core Data 121
- Offset: 1Ah-1Bh 122
- 7.4.3.4 Cache Data 124
- Offset: 29h-2Ah 125
- 2Bh-2Ch 125
- 2Dh-2Eh 125
- 7.4.3.5 Package Data 126
- 7.4.3.6 Part Number Data 127
- 38h-3Eh 128
- 3Fh-4Ch 128
- 4Dh=54h 128
- 55h-6Eh 128
- 71h-72h 129
- 7.4.3.8 Feature Data 130
- 7.4.3.9 OD: Other Data 131
- 7.4.4 Checksums 132
- 7.4.5 Scratch EEPROM 132
- 8 Debug Tools Specifications 133
- Debug Tools Specifications 134
- 9.1 Introduction 135
- 9.2 Thermal Specifications 135
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