Low Voltage Intel
®
Xeon
™
Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz
36 Datasheet
Figure 11. System Bus Reset and Configuration Timing Waveform
Figure 12. Power-On Reset and Configuration Timing Waveform
B2276-01
Reset
Configuration
A[31:3],
SM#, INIT#
BCLK
Tt
Ty
Tx
Tv
Tw
Valid
Configuration
BR0#
Notes:
Tv = T13 (RESET# Pulse Width)
Tw = T45 (Reset Configuration Signals Setup Time)
Tx = T46 (Reset Configuration Signals A[31:3], SM#, and INIT# Hold Time
Ty = T47 (Reset Configuration BR0# Hold Time)
Valid
BLCK
Ta = T37 (PWRGOOD Inactive Pluse Width)
VCC
PWRGOOD
RESET#
T
b
T
a
Tb = T36 (PWRGOOD to RESET# de-assertion time)
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