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Low Voltage Intel
®
Xeon
™
Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz
Datasheet 47
1.45 -0.15 10.00 10.00 10.00
1.40 -0.10 10.00 10.00 10.00
1.35 -0.05 10.00 10.00 10.00
Table 24. Common Clock (400 MHz) AGTL+ Signal Group
Overshoot/Undershoot Tolerance
Absolute
Maximum
Overshoot (V)
Absolute
Maximum
Undershoot (V)
Pulse Duration (ns)
AF = 1
Pulse Duration
(ns) AF = 0.1
Pulse Duration (ns)
AF = 0.01
1.70 -0.40 1.68 16.72 20.00
1.65 -0.35 5.00 20.00 20.00
1.60 -0.30 14.64 20.00 20.00
1.55 -0.25 20.00 20.00 20.00
1.50 -0.20 20.00 20.00 20.00
1.45 -0.15 20.00 20.00 20.00
1.40 -0.10 20.00 20.00 20.00
1.35 -0.05 20.00 20.00 20.00
NOTES:
1. These specifications are measured at the processor pad.
2. BCLK period is 10 ns.
3. WIRED OR processor signals may tolerate up to 1 V of overshoot/undershoot.
4. AF is referenced to BCLK[1:0]
Table 25. 400 MHz Asynchronous GTL+, PWRGOOD, and TAP Signal Groups
Overshoot/Undershoot Tolerance (Sheet 1 of 2)
Absolute
Maximum
Overshoot (V)
Absolute
Maximum
Undershoot (V)
Pulse Duration (ns)
AF = 1
Pulse Duration
(ns) AF = 0.1
Pulse Duration (ns)
AF = 0.01
1.70 -0.40 5.04 50.16 60.00
1.65 -0.35 14.99 60.00 60.00
1.60 -0.30 43.92 60.00 60.00
1.55 -0.25 60.00 60.00 60.00
1.50 -0.20 60.00 60.00 60.00
NOTES:
1. These specifications are measured at the processor pad.
2. These signals are assumed in a 33 MHz time domain.
Table 23. Source Synchronous (400 MHz) AGTL+ Signal Group
Overshoot/Undershoot Tolerance
Absolute
Maximum
Overshoot (V)
Absolute
Maximum
Undershoot (V)
Pulse Duration
(ns) AF = 1
Pulse Duration (ns)
AF = 0.1
Pulse Duration (ns)
AF = 0.01
NOTES:
1. These specifications are measured at the processor pad.
2. Assumes a BCLK period of 10 ns.
3. AF is referenced to associated source synchronous strobes.
- Low Voltage Intel 1
- Processor at 1
- 1.60 GHz, 2.0 GHz and 2.4 GHz 1
- 2 Datasheet 2
- Contents 3
- Revision History 7
- 8 Datasheet 8
- 1.0 Introduction 9
- 1.1 Terminology 10
- 1.2 State of Data 11
- 1.3 References 11
- 12 Datasheet 12
- 2.0 Electrical Specifications 13
- Decoupling 14
- 2.5 PLL Filter 15
- Figure 1. Typical V 16
- Power Distribution 16
- 2.6 Voltage Identification 17
- 18 Datasheet 18
- 2.7 Reserved Or Unused Pins 19
- 2.8 System Bus Signal Groups 19
- 20 Datasheet 20
- 2.9 Asynchronous GTL+ Signals 21
- 2.10 Maximum Ratings 21
- 22 Datasheet 22
- Datasheet 23 23
- Figure 3. Low Voltage Intel 24
- Processor Voltage and 24
- Datasheet 25 25
- 26 Datasheet 26
- Datasheet 27 27
- 28 Datasheet 28
- Datasheet 29 29
- 30 Datasheet 30
- Datasheet 31 31
- 32 Datasheet 32
- Datasheet 33 33
- 34 Datasheet 34
- Datasheet 35 35
- 36 Datasheet 36
- Figure 15. THERMTRIP# to V 37
- Power Down 38
- Power Up 38
- Datasheet 39 39
- 40 Datasheet 40
- Noise Margi 41
- 42 Datasheet 42
- Datasheet 43 43
- 3.3.4 Activity Factor 44
- Specifications 45
- 46 Datasheet 46
- Datasheet 47 47
- 48 Datasheet 48
- Undershoot Tolerance 49
- 50 Datasheet 50
- 4.0 Mechanical Specifications 51
- 4.1 Mechanical Specifications 52
- Figure 25. Low Voltage Intel 53
- 54 Datasheet 54
- Datasheet 55 55
- 56 Datasheet 56
- 4.3 Insertion Specifications 57
- 4.4 Mass Specifications 57
- 4.5 Materials 57
- 4.6 Markings 58
- 4.7 Processor Pin-Out Diagram 58
- Datasheet 59 59
- 60 Datasheet 60
- 5.1 Processor Pin Assignments 61
- 62 Datasheet 62
- Datasheet 63 63
- 64 Datasheet 64
- Datasheet 65 65
- 66 Datasheet 66
- Datasheet 67 67
- 68 Datasheet 68
- Datasheet 69 69
- 70 Datasheet 70
- Datasheet 71 71
- 72 Datasheet 72
- Datasheet 73 73
- 74 Datasheet 74
- Datasheet 75 75
- 76 Datasheet 76
- Datasheet 77 77
- 78 Datasheet 78
- 5.2 Signal Definitions 79
- 80 Datasheet 80
- 82 Datasheet 82
- Datasheet 83 83
- 84 Datasheet 84
- Datasheet 85 85
- 86 Datasheet 86
- Datasheet 87 87
- 88 Datasheet 88
- 6.0 Thermal Specifications 89
- 90 Datasheet 90
- Datasheet 91 91
- 92 Datasheet 92
- 7.0 Features 93
- 94 Datasheet 94
- 7.2.5 Sleep State—State 5 95
- 7.3 Thermal Monitor 96
- 7.4 Thermal Diode 97
- 98 Datasheet 98
- Debug Port Design Guide 99
- 100 Datasheet 100
- 9.0 Appendix A 101
- 102 Datasheet 102
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